The present invention relates to a semiconductor integrated circuit device and to technology for its production. In particular, the invention relates to technology that can be effectively adapted to a semiconductor integrated circuit device having an SRAM (static random access memory).
The SRAM which works as a semiconductor storage device has memory cells each constituted by a flip-flop circuit and two transfer MISFETs (metal insulator semiconductor field-effect transistors) at a point where a word line and a pair of complementary data lines intersect each other.
The flip-flop circuit is constituted by, for example, two drive MISFETs and two high-resistance load elements, and stores data of one bit. Gate electrodes of the two drive MISFETs are connected to the drain regions of the other drive MISFETs, respectively, and the source regions are fixed to ground potential (GND). The two high-resistance load elements are connected at their ends on one side to the drain regions of the drive MISFETs, and are subjected at their ends on the other side to a power source voltage (Vcc).
The source region of one transfer MISFET is connected to the drain region of one drive MISFET, and the source region of the other transfer MISFET is connected to the drain region of the other drive MISFET. Complementary data lines are connected to the drain regions of the two transfer MISFETs, and the word line is connected to respective gate electrodes.
In a memory cell of an SRAM disclosed in U.S. Pat. No. 4,853,894, the gate electrodes of drive MISFETs and transfer MISFETs and the word line are constituted by a polycrystalline silicon film of a first layer, and the high-resistance load elements are constituted by a polycrystalline silicon film of a second layer. Ground voltage lines for fixing the source regions of drive MISFETs to ground potential are constituted by a polycrystalline silicon film of a third layer, and the data line is constituted by an aluminum (Al) wiring formed on the ground voltage lines.
In this SRAM, the high-resistance load elements are electrostatically shielded by the ground voltage lines, so that the amounts of electric current flowing into the high-resistance load elements are prevented from changing. Moreover, a capacitance element is constituted by the ground voltage lines, part of the second polycrystalline silicon film layer (low-resistance portions at both ends of the high-resistance load elements) of the second layer, and an insulating film therebetween. The electric charge of the capacitance element is fed to a charge-accumulating node of the memory cell to improve resistance against soft error caused by a particles. The SRAM having capacitance element has also been disclosed in, for example, U.S. Pat. No. 4,805,147.
Owing to their high-speed performance, the SRAMs of this kind have been used for main memories and cache memories of computers in recent years. To realize the operation at higher speeds, however, it is essential to employ wiring of a multilayer structure. Concretely speaking, the data lines must be constituted by a low-resistance metal wiring such as Al wiring, and the word lines and the ground voltage lines constituted by a polycrystalline silicon film must be shunted by a low-resistance metal wiring, in order to increase the speed of data writing operation and reading operation.
In the SRAM disclosed in the above-mentioned publication, for example, an aluminum wiring of a double-layer structure is used to shunt the word lines and the ground voltage lines. The main word line (word line for shunting) and the ground voltage lines for shunting are constituted by the Al wiring of the first layer, and the data lines are constituted by the Al wiring of the second layer.
Here, the main word lines are provided at a rate of, for example, one line per 4 bits of memory cells, and are connected to the word lines at a word decoder neighboring the memory array. On the other hand, the ground voltage line for shunting and the ground voltage line are connected together for each memory cell through a connection hole formed in an insulating film that isolates the two from each other. When the data lines are constituted by the Al wiring of the second layer, the connection hole for connecting the drain region of the transfer MISFET and the data line together possesses an increased aspect ratio which deteriorates reliability in the conduction of data line inside the connection hole. Accordingly, the pad layers are constituted by the Al wiring of the first layer, and the drain regions of the transfer MISFETs and the data lines are connected together via the pad layers. An SRAM having a two-layer Al structure has been disclosed in, for example, U.S. Pat. No. 5,122,857.